China's Chip Production Faces Rising Costs as DUV Workarounds Limit Efficiency
Multiple patterning allows Chinese manufacturers to bypass EUV restrictions, but the method increases defect rates and reduces the number of usable chips per wafer.
By Kwame Silva ·
Chinese semiconductor manufacturers are continuing to produce advanced processors using older deep ultraviolet lithography equipment, a strategy that works but increases production expenses and complexity.
Export controls have prevented ASML from shipping its extreme ultraviolet machines to China. ASML is the sole producer of these tools, which use 13.5-nanometer light to print the finest features on modern chips. Without access to this technology, Chinese firms rely on deep ultraviolet systems. Some analysts estimate this creates a five-year gap in manufacturing capability between China and Western rivals.
Despite these constraints, Chinese firms have achieved notable progress. A 2023 teardown of the Huawei Mate 60 Pro revealed that its Kirin 9000S processor was manufactured by Semiconductor Manufacturing International Corporation using a second-generation 7-nanometer process. Recent analysis suggests the company has moved its process closer to 5-nanometer density, though it still lags behind leaders like TSMC and Samsung.
The method relies on multiple patterning. Instead of printing a complex layer in a single step, engineers break the design into simpler patterns and build the layer incrementally. Chris Mack, co-founder and CTO of Fractilia, noted that industry standards suggest three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, when a process requires four masks, EUV becomes the more economical option.
The additional steps introduce quality challenges. Each new pattern must align precisely with previous layers, leading to accumulated errors. Designers often add extra space around features to compensate, which enlarges the chip and reduces the number of dies per wafer. Since wafers cost tens of thousands of dollars, this reduction in yield is a major financial factor. Mack stated, "You don't sell wafers, you sell die."
Memory production data illustrates the efficiency gap. A June report from Morgan Stanley estimated that Chinese DRAM maker ChangXin Memory Technologies produces only one-third as many bits per wafer as Western competitors. The bank described lithography access as a hard ceiling for Chinese memory development. Mack added that process node labels like 5nm or 3nm have limited meaning without context, and SMIC's N+3 process remains less scaled than established 5nm nodes from Samsung and TSMC.
Deep ultraviolet technology still has room for advancement. Micron developed its 1-alpha DRAM without EUV by using tight process control and multiple patterning. Mack said Micron pushed 193-nanometer technology farther than other memory makers. Morgan Stanley believes ChangXin can achieve its planned move to 1-alpha DRAM for HBM3e applications without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade.
While DUV can go further, it has limits. Micron eventually switched to EUV for its 1-gamma DRAM, which offers more than 30 percent greater bit density per wafer than the previous generation. Mack said he would be hard pressed to believe a 3-nanometer or 2-nanometer node could be economically viable without EUV.
Chinese chipmakers plan to continue expanding capacity while accepting larger dies and lower yields. Morgan Stanley projects that ChangXin will remain on 1-alpha DRAM without EUV but will increase its share of global DRAM bit supply from 14 percent in 2026 to 16 percent in 2028. The bank also expects China's AI chip self-sufficiency to rise from 42 percent in 2025 to 70 percent by 2030, with EUV, HBM, and advanced software remaining persistent gaps.
